71 FPGAs key to the success of PCB printer Lunaris
In 2009 Mutracx demonstrated his Lunaris inkjet technology to print the inner layers of a Printed Circuit Board (PCB). Since then, the Océ spinoff worked hard to make the technology ready for the market. 3T has developed a real-time data path in which 71 FPGAs provide the control of the printheads for this machine.
The Lunaris is a 100 percent replacement of conventional lithographic systems, in order to print the inner layers of a PCB. Unlike the traditional production method, the machine of Mutracx sprays the etch resist directly on the copper substrate. Within one minute there will be two billion drops sprayed out, covering one side of the circuit board. The bare metal is then etched and the protective layer is stripped of the remaining tracks. The advantages of this approach: the coper does not need to get any photosensitive coating, there is no separate mask needed, not need for light exposure, and the resist does not have to develop. Traditionally, the process takes thirteen steps to get a pattern on the copper, in which every step requires a different machine. The Lunaris approach does this all at once, with a system that seamlessly connects to the existing etching and stripping baths after this process step.
To get the drops on the copper substrate using the Mutracx machine, printheads with 256 nozzles per head are required which are synchronously fed with 256 bit imagelines. These nozzles are divided into four groups of 64, controlled by a quartet of ASICs that regulate the drop formation by generating pressure waves in the nozzle by means of a piezo-element. The piezo can also set to a listening mode, in which it changes from an actuator into a sensor that measures the status of the nozzle. This makes it possible to detect failing nozzles and compensate for them dynamically using redundant headers. For this, the system uses the real-time Predict algorithm, which has its roots at Océ. Because the piezo can not be simultaneously actuator and sensor, Mutracx has chosen to divide the heads into groups of three: while one prints, the other two are measured. The three heads are physically placed behind each other.
3T has developed the real-time data path that transports the PCB image from the machine PC to the sixty print heads and ensures that all droplets arrive at the correct position. Main part of this path is the bus master, consisting of a Xilinx Virtex 6 FPGA. The busmaster is connected via PCI Express to the PC and has a DDR2 memory to cache the PCB image bitmap. From there, the image data is distributed over ten Predict routers, each of which contains a Xilinx Virtex 5 FPGA with a dynamic compensation algorithm. Each router controls six head controllers, using a Xilinx Spartan 6, which in turn make sure that the heads are operating correctly.
In total, the data path has 71 Xilinx FPGAs, all of which are remotely programmable. For this system, we first set the architecture and the specifications together with the Mutracx System Architect. We then developed all the firmware as well as the electronics for the routers and the head controllers. On forehand we have analyzed the signal integrity of the various hardware modules. We also have them subjected to design-for-test (DfT) and design-for-manufacturability (DfM) analysis. We have also written a shared library and a test application for Linux.
Real-time control is critical in order to ensure that every drop of ink is fired at the right time. After all, one miss can lead to rejection of the whole PCB. The data path therefore uses an external print synchronizing signal (Y-sync) for the firing of drops at up to 100 kHz. This provides a continuous flow of data of about 4 Gbits per second. The jitter, that the shooting of droplets may exhibit relative to the Y-sync signal, may be up to 250 ns. The latency of the data path is dealt with in software by adjusting the PCB bitmap on forehand. In order to be able to the meet the PCB specifications, it is necessary that we measure the nozzle status as input for the compensation algorithms. This provides a data stream of 5 Gbits per second from the print heads back to the PC.
The PCI Express interface between the PC and bus master does not guarantee the 4 Gbit/s needed for bitmap transport. This is partly because the PC is already preparing the next PCB image during printing and different software processes on the PC share the memory bandwidth. We have therefore chosen to provide the bus master with 16 GB of DDR2 memory (four SODIMMs of 4 Gbytes). With this, the system can cache the complete bitmap before the actual printing begins. By doing so, the real-time functionality is fully implemented in hardware. In the future, we want to look at the ability to cache only a part of the bitmap in advance. During the print job, the system then streams the remaining data to the bus master and the software on the PC can prepare the next image and save it in the PC memory. Doing so, we could reduce the DDR2 memory to 8 or even 4 Gbytes.
For the first Lunaris product, 3T developed a real-time data path using one Virtex 6, ten Virtex 5 and sixty Spartan 6 Xilinx FPGAs.
For the control of the four SODIMM modules, we needed just as many Xilinx DDR2 IP-cores. However, a Virtex 6 device does not support multi-core DDR2-IP. Therefore, we have to adapt the single core DDR2 architecture manually. For the PCI Express implementation, we have used a hard coded Endpoint in the Virtex 6 in conjunction with IP block from the PLDA supplier that gives the DMA support. The DMA engine provides eight channels for the PCB bitmap to be transported to the heads and bring back the measurement data to the PC. Ten high-speed serial links run between the bus master and the routers, each one has a RocketIO GTX transceiver in Virtex 6 connecting it to a RocketIO MGT transceiver of the Virtex 5. The required bandwidth is 1 Gbit/s per channel.
Synchronously with the Y-sync signal, the bus master sends print data frames to the routers. The low-level communication protocol is the Xilinx Aurora protocol. The corresponding IP block can send large amounts of data with minimal overhead. The protocol uses special clock offset commands to align the reference clocks of the transmitter and receiver to each other and compensate for drift. These have priority over the normal data frames. There is a relatively large amount of jitter on the transport of these frames and in the end to the printing. However, Aurora provides opportunities to control the sending of clock compensation commands. We used that to prevent clock compensation during the transmission of print data frames.
The routers provide the frames to the printhead controller via a dedicated protocol that we have developed based on LVDS. This interface requires a bandwidth of 200 Mbit/s. The advantage of LVDS is that there are no high-speed transceivers required. This makes it possible to use the cheaper Spartan 6 LX version in the print head controller. Since there are sixty of these in the machine, this provides a significant cost saving.
The printhead controller translates the incoming print data frames to the instructions for controlling the nozzles. These commands are passed through via separate SPI interfaces to the four ASICS. The commands to initiate the status measurements and to read out the ink level, the temperature of the ink, head and, ASIC, are also running through these links. The printhead controller controls two stepper motors for the mechanical adjustment of the head in x-and z-direction. Deviations in the y-direction can be compensated for by software by changing the PCB bitmap.
All interfaces, from PC to the print head controller, have been made full-duplex in order to return the nozzle status information during printing. The Predict algorithm in the router FPGA dynamically compensates for failing nozzles through redundant heads. Then the data moves back to the PC for any further offline analysis. Except for the Predict algorithm there is the Paint algorithm, which also originates from Océ. This software-implemented algorithm uses the status information in order to statically compensate the PCB bitmap prior to printing.
With Modelsim we have tested the complete data path functionally in a simulation environment on a PC. The supplier of the PCI Express IP provides comprehensive simulation libraries for PCI Express hosts, which include memory-mapped IO registers to read and write and support DMA transfers and interrupts. With this we also looked closely to the control part from software. Also the DDR2 modules are available in simulation models. This we used for testing the complete data flow from the PC via the DDR2 memory to the routers. We also made a functional model of the router which is able to simulate the printing and can generate Paint and Predict data. We have limited the PCB bitmaps to a number of image lines in simulation.
For verification of the printed bitmap and the Predict algorithm, we have added special test functionality to the data path. This makes it possible to set one print group in test mode, in which all the printed image lines of the group are logged, provided with a time stamp and streamed to the PC. With this image data and time information, we can reconstruct the bitmap in software and compare it with the original. For the three print head controllers that are in test mode, it is also possible to set nozzle status patterns. Instead of measuring the nozzles, the system then uses these parameters to verify the Paint and Predict algorithms. Combined with the image data log, it is possible to qualify the data path, without the need to have any print heads physically connected.
The real market confrontation is this summer. Then Mutracx will perform beta testing with several customers.
Ronald Grootelaar, consulting engineer at 3T in Enschede.
Source: Bits & Chips, 31 March 2011